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  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
Design of High-Performance CMOS Voltage-Controlled Oscillators

Design of High-Performance CMOS Voltage-Controlled Oscillators

Liang Dai
Harjani, Ramesh

Hardcover

Series: The Springer International Engineering and Computer Science, Book 708

Technology & Engineering

ISBN10: 1402072384
ISBN13: 9781402072383
Publisher: Springer Nature
Published: Oct 31 2002
Pages: 158
Weight: 0.97
Height: 0.66 Width: 6.84 Depth: 8.96
Language: English
Design of High-Performance CMOS Voltage-Controlled Oscillators presents a phase noise modeling framework for CMOS ring oscillators. The analysis considers both linear and nonlinear operation. It indicates that fast rail-to-rail switching has to be achieved to minimize phase noise. Additionally, in conventional design the flicker noise in the bias circuit can potentially dominate the phase noise at low offset frequencies. Therefore, for narrow bandwidth PLLs, noise up conversion for the bias circuits should be minimized. We define the effective Q factor (Qeff) for ring oscillators and predict its increase for CMOS processes with smaller feature sizes. Our phase noise analysis is validated via simulation and measurement results.

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