Open Daily: 10am - 10pm | Alley door pickup 10am - 7pm 3038 Hennepin Ave Minneapolis, MN
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  • Open Daily: 10am - 10pm
    Alley-side Pickup: 10am - 7pm

    3038 Hennepin Ave Minneapolis, MN
    612-822-4611

Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
High Resolution and Low Jitter Full Custom Adpll Architectures

High Resolution and Low Jitter Full Custom Adpll Architectures

Jahangir, Mohd Ziauddin
Shekar, P. Chandra

Paperback

Technology & Engineering

ISBN10: 6208445582
ISBN13: 9786208445584
Publisher: LAP Lambert Academic Publishing
Published: May 19 2025
Pages: 216
Weight: 0.65
Height: 0.49 Width: 6.00 Depth: 9.00
Language: English
All digital PLLs are being considered as an effective replacement due to high immunity of digital circuits to PVT variations. However, ADPLLs suffer from the problem of low resolution and high jitter/ phase noise apart from fundamental problems of complex design procedures. It was found through literature surveys and experimental verifications that there are still some challenges related to resolution, jitter/phase noise that need to be addressed, in the existing ADPLLs. Similarly, it was also found that there is a shortcoming in the models used to describe ADPLLs. In this regard, an extensive classification of existing ADPLL architectures was made. Some of the architectures found in literature were critically examined by redesigning and simulation verification at various levels of design with a wide set of simulation/emulation tools. Comparative analysis was done and shortcomings in each architecture were critically identified. Methods to improve resolution and phase noise were proposed and verified using simulation.

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