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Open Daily: 10am - 10pm | Alley-side Pickup: 10am - 7pm
3038 Hennepin Ave Minneapolis, MN
612-822-4611
LOW POWER ADDER DESIGN for VLSI

LOW POWER ADDER DESIGN for VLSI

Paperback

Business General

ISBN10: 6208847796
ISBN13: 9786208847791
Publisher: Scholars' Press
Published: Jun 27 2025
Pages: 52
Weight: 0.18
Height: 0.12 Width: 6.00 Depth: 9.00
Language: English
This wok proposes an energy efficient approximate adder that provides low power high performance addition without severe quality degradation. The proposed adder introduces area efficient approximate logic that is used to adder least significant bits of the adder. The effectiveness of the adder is analyzed over the well known accurate and approximate adders by implementing on Tanner and MATLAB. The simulation result shows that proposed adder outperform over the existing adder and can be effectively applied to the applications that can tolerate small amount of error.

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Jain, Manish

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Business General